A flash memory may not lose stored data even after powered down, so it is especially adapted to a field of storage components in mobile communications, computer, etc. Some flash memories also have a high-density memory capacity and may be used in large-capacity removable memory media and other applications. A SONOS flash memory has a silicon-oxide-nitride-oxide-silicon structure and comprises a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer. In the SONOS flash memory, a charge (an electron or a hole) is injected into a silicon nitride layer through a tunneling oxide layer by using a quantum tunneling or hot carrier injection effect, and trapped by charge traps in the silicon nitride layer, thus changing a threshold voltage of a device cell and achieving data storage.
FIG. 1 is a schematic view of a conventional SONOS flash memory array based on a NAND serial structure. A series of SONOS memory modules are connected together, and SONOS memory cell transistors are connected to a plurality of bit lines 101 via a drain selection transistor (DST) respectively. A source of the memory cell transistor is connected to a common source line (SL) 103 via a source selection transistor (SST). Gates of the memory cell transistors are connected together via a series of polysilicon routings to form a word line (WL) 105. The NAND structure memory has a high-capacity memory feature of a NAND structure, and performs programming and erasing operations by using a FN tunneling mechanism. However, as a requirement for large capacity and high density of a memory increases daily, a conventional planar NAND array flash memory may not be endlessly scaled down because of a limit of the device dimension. Therefore, a capacity and a density of the planar memory may not be further improved, so a three-dimensional memory conception is proposed.
FIG. 2 is a sectional view of a conventional vertical-trench type SONOS memory cell. For example, a SONOS memory cell described in Patent Application No. 200410009676.3 comprises a p-type substrate, a p-type well, a deep trench, a n-type doping region on bottom of the deep trench, and a drain region and a source region on each side of the deep trench. Inside the deep trench there is a gate structure consisting of a silicon dioxide tunneling dielectric layer, a charge trapping layer, an insulating dielectric layer and a polysilicon control gate. During a programming operation, if the drain region is to be programmed, a positive voltage is applied to the drain region, the source region is floated or grounded, and a negative voltage is applied to the polysilicon control gate. And if the source region is to be programmed, a positive voltage is applied to the source region, the drain region is floated or grounded, and a negative voltage is applied to the polysilicon control gate. During an erasing operation, a positive voltage is applied to the polysilicon control gate, and the source region and the drain area are floated or grounded. During a reading operation, if an information on the source region is to be read, a positive voltage is applied to the drain region, the source region is grounded, and a positive or negative voltage is applied to the control gate. And if an information on the drain region is to be read, a positive voltage is applied to the source region, the drain region is grounded, and a positive or negative voltage is applied to the polysilicon control gate. The structure performs a programming operation according to a band-to-band tunneling hot hole injection principle, and performs an erasing operation by channel F-N erasing. The structure with a vertical channel is conducive to a three-dimensional integration.
Based on a concept of a vertical channel memory cell transistor, a vertical series SONOS flash memory array structure is proposed in US 20100200906 by M. Kidoh et al. in 2010. FIG. 3 is a perspective view of a conventional vertical series SONOS flash memory structure. Two adjacent NAND memory modules are connected via a bottom CP to form a “U-shaped pipe”, in which CP is a transistor controlled by a bottom gate electrode. One end of the “U” shaped string is connected to a bit line BL, and the other end thereof is connected to a source line SL. BL and SL are formed by different layers of metal routings. Both a selection gate and a control gate of a transistor are located below the BL and SL. The control gates (WL) are spaced apart from each other by a slit, and have a comb-like shape. A memory dielectric comprises a blocking oxide layer, a charge trapping layer and a tunneling oxide layer. By applying different combinations of voltages to the bit line, the word line and the source line, a programming, erasing or reading operation for one or more memory cell transistors in the array may be achieved.
The shortcomings of the prior art are that the vertical series SONOS flash memory process and control method in FIG. 3 are complex, which urgently needs to be improved.